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HCTS08MS
August 1995
Radiation Hardened Quad 2-Input AND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14 TOP VIEW
A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3
Features
* 3 Micron Radiation Hardened SOS CMOS * Total Dose 200K RAD(Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) * Dose Rate Survivability: >1 x * Dose Rate Upset >10
10
1012
Rads (Si)/Sec
RAD(Si)/s 20ns Pulse
* Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * LSTTL Input Compatibility - VIL = 0.8V - VIH = VCC/2 * Input Current Levels Ii 5A at VOL, VOH
A1 B1
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW
1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3
Description
The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input AND Gate. A high on both inputs force the output to a High state. The HCTS08MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS08MS is supplied in a 14 lead Ceramic Flatpack Package (K suffix) or a 14 lead SBDIP Package (D suffix).
Y1 A2 B2 Y2 GND
TRUTH TABLE INPUTS An Bn L H L H OUTPUTS Yn L L L H
Ordering Information
PART NUMBER HCTS08DMSR TEMPERATURE RANGE -55oC to +125oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample PACKAGE 14 Lead SBDIP
L L H H
NOTE: L = Logic Level Low, H = Logic level High 14 Lead Ceramic Flatpack 14 Lead SBDIP
HCTS08KMSR
-55oC
to
+125oC
Functional Diagram
(1, 4, 9, 12) An (3, 6, 8, 11) Yn (2, 5, 10, 13) Bn
HCTS08D/ Sample HCTS08K/ Sample HCTS08HMSR
+25oC
+25oC
Sample
14 Lead Ceramic Flatpack Die
+25oC
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518842 2136.2
DB NA
Specifications HCTS08MS
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package . . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W Maximum Package Power Dissipation at +125oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 2.25V, IOL = 50A, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOL = 50A, VIL = 0.8V Output Voltage High VOH VCC = 4.5V, VIH = 2.25V, IOH = -50A, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOH = -50A, VIL = 0.8V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 10 200 0.1 UNITS A A mA mA mA mA V
PARAMETERS Quiescent Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -0.5 -5.0 4.0
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC, +125oC, -55oC
+0.5 +5.0 0.5
A A -
Noise Immunity Functional Test
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 2)
7, 8A, 8B
NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 2
518842
Specifications HCTS08MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 TPLH VCC = 4.5V 9 10, 11 NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 2 2 2 MAX 18 20 20 22 UNITS ns ns ns ns
PARAMETER Input to Output
SYMBOL TPHL
(NOTES 1, 2) CONDITIONS VCC = 4.5V
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation SYMBOL CPD CONDITIONS VCC = 5.0V, f = 1MHz NOTES 1 1 Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 1 Output Transition Time TTHL TTLH VCC = 4.5V 1 1 NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TEMPERATURE +25oC +125oC, -55oC +25oC +125oC +25oC +125oC MIN MAX 45 80 10 10 15 22 UNITS pF pF pF pF ns ns
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETERS Quiescent Current Output Current (Sink) SYMBOL ICC IOL (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V at 200K RAD, IOL = 50A VCC = 4.5V and 5.5V, VIH = VCC/2, VIL = 0.8V at 200K RAD, IOH = -50A VCC = 5.5V, VIN = VCC or GND TEMPERATURE +25oC +25oC MIN 4.0 MAX 0.2 UNITS mA mA
Output Current (Source)
IOH
+25oC
-4.0
-
mA
Output Voltage Low
VOL
+25oC
-
0.1
V
Output Voltage High
VOH
+25oC
VCC -0.1
-
V
Input Leakage Current
IIN
+25oC
-5.0
+5.0
A
Spec Number 3
518842
Specifications HCTS08MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) 200K RAD LIMITS PARAMETERS Noise Immunity Functional Test Input to Output SYMBOL FN (NOTES 1, 2) CONDITIONS VCC = 4.5V, VIH = 2.25V, VIL = 0.8V at 200K RAD, (Note 3) VCC = 4.5V VCC = 4.5V TEMPERATURE +25oC MIN MAX UNITS -
TPHL TPLH
+25oC +25oC
2 2
20 22
ns ns
NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. 3. For functional tests, VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
PARAMETER ICC IOL/IOH
DELTA LIMIT 3A -15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS COMFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A (Note 1) Subgroup B5 Subgroup B6 Group D NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised. 2. Table 5 parameters only. MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 TESTED 1, 7, 9 1, 7, 9, 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, 1, 7, 9 1, 7, 9 1, 2, 3, (Note 2) RECORDED 1 (Note 2) 1, (Note 2)
TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1)
Spec Number 4
518842
Specifications HCTS08MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONDITIONS (Note 1) 3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12, 13 14 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14 -
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2) 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10, 12, 13 -
NOTES: 1. Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in. 2. Each pin except VCC and GND will have a resistor of 1K 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 3, 6, 8, 11 GROUND 7 VCC = 5V 0.5V 1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 5
518842
HCTS08MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
Spec Number 6
518842
HCTS08MS AC Timing Diagrams
VIH VS VIL TPLH TPHL VOH VS VOL OUTPUT CL = 50pF RL = 500 INPUT CL RL
AC Load Circuit
DUT TEST POINT
FIGURE 2
VOH TTLH 80% VOL 20% 80% 20% TTHL
OUTPUT
FIGURE 1 AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCTS 4.50 3.00 1.30 0 0 UNITS V V V V V
Spec Number 7
518842
HCTS08MS Die Characteristics
DIE DIMENSIONS: 87 x 88 mils 2.20 x 2.24mm METALLIZATION: Type: SiAl Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils
Metallization Mask Layout
HCTS08MS
A1 (1) VCC (14) B4 (13)
B1 (2)
(12) A4
Y1 (3)
(11) Y4
A2 (4)
(10) B3
B2 (5) (9) A3
(6) Y2
(7) GND
(8) Y3
Spec Number 8
518842
HCTS08MS Packaging
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS
c c1 D eA E e eA eA/2 L Q S1 S2
e
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 9
518842
HCTS08MS Packaging (Continued)
A
K14.B
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.003 0.003 0.235 0.125 0.030 MAX 0.115 0.022 0.019 0.009 0.007 0.390 0.260 0.290 MILLIMETERS MIN 1.14 0.38 0.38 0.08 0.08 5.97 3.18 0.76 1.27 BSC 0.20 6.86 0.25 0.13 14 0.38 9.40 0.51 0.04 MAX 2.92 0.56 0.48 0.23 0.18 9.91 6.60 7.11 NOTES 3 3 7 2 8 6 Rev. 0 6/14/94
e
PIN NO. 1 ID AREA
A
-A-
-B-
D
A b
S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS
b1 c c1 D E E1 E2 E3 e k L
0.050 BSC 0.008 0.270 0.010 0.005 14 0.015 0.370 0.020 0.0015
BASE METAL b1 M M (b) SECTION A-A
(c)
Q S1 M N
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
Spec Number 10
518842

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